The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure that includes an inner spacer structure that is positioned between each semiconductor nanosheet of a vertical stack of semiconductor nanosheets, wherein the inner spacer structure further separates a functional gate structure that surrounds each semiconductor nanosheet from a source/drain (S/D) semiconductor material structure that is present on each side of the functional gate structure. The present application also relates to a method of forming such a semiconductor structure.
As semiconductor integrated circuits (ICs) or chips become smaller, vertically stacked semiconductor nanosheets, which are two-dimensional nanostructures in which the vertical thickness is substantially less than the width, are increasingly being used. Semiconductor nanosheets are seen as a feasible device option for 7 nm and beyond scaling of semiconductor devices. Vertically stacked semiconductor nanosheets provide area efficiency and can provide increased drive current within a given layout.
The general process flow for semiconductor nanosheet formation involves the formation of a material stack that contains sacrificial layers of silicon germanium between silicon nanosheets. After removing the sacrificial layers, vertically stacked and suspended silicon nanosheets are provided. A functional gate structure can be formed above and below each silicon nanosheet to provide a gate-all-around design.
In the formation of semiconductor nanosheet containing devices, there is a need for providing an inner spacer structure for disconnecting the sacrificial layers from the epitaxy that forms the source/drain (S/D) semiconductor material structures, and to provide a more controllable means for recessing the sacrificial layers.